An inverter system capable of high level control by a microcontroller has been widely used for controlling a motor which is used in household electrical appliances, such as an air conditioner or a refrigerator, in order to improve energy-saving performance. On the other hand, with practical use of a wide band gap semiconductor element such as SiCFET or GaNFET, application to an inverter circuit has been studied in an effort to aim efficiency improvement by low on-resistance and high frequency characteristics thereof.
FIG. 6 shows an example of a circuit configuration of a conventional inverter circuit. FIG. 6 is an example of a configuration of an inverter circuit INV which is configured with a driver circuit 30, power switching elements of an n-type MOSFET 7a and 7b, a diode 8, and a condenser 9. The driver circuit 30 has a function of a level shift circuit.
In the driver circuit 30, a power source terminal VCC and a ground terminal VSS which perform supplying externally, a control input terminal Inh on a high-side circuit 36 side, a control input terminal Inl on a low side, a positive voltage power source terminal Vb, a reference power source terminal Vs and an output terminal Vh on the high-side circuit 36 side, and an output terminal V1 on the low side are provided, respectively. The power source terminal VCC and the ground terminal VSS of the driver circuit 30 are connected to a power source terminal VCC and a ground terminal VSS of the inverter circuit INV, respectively.
A control input signal on the high-side circuit 36 side, which is input by the control input terminal Inh, is connected to an input terminal IN of a pulse generating circuit 31, and a first pulse with a pulse width of around 100 ns is generated from a first output terminal OUT1 after rising of the control input signal and a second pulse with a pulse width of around 100 ns is generated from a second output terminal OUT2 after falling of the control input signal, respectively.
FIG. 7 shows one example of a circuit configuration of the pulse generating circuit 31. The pulse generating circuit 31 is configured by including six inverters 41a, 41b, 41c, 41d, 41e and 41f which are cascade-connected, two NAND circuits 42a and 42b, two inverters 43a and 43b, and two condensers 44a and 44b for pulse width setting. An input of the head inverter 41a is connected to the input terminal IN, and when output nodes of the inverters 41a, 41b, 41c, 41d, 41e and 41f are set as N1, N2, N3, N4, N5 and N6 in order from head, respectively, one end each of the condensers 44a and 44b is grounded, the other ends thereof are connected to the nodes N3 and N4, respectively, the nodes N2 and N5 are connected to two inputs of the NAND circuit 42a, respectively, the nodes N1 and N6 are connected to two inputs of the NAND circuit 42b, respectively, outputs of the NAND circuits 42a and 42b are connected to inputs of the inverters 43a and 43b, respectively, and outputs of the inverters 43a and 43b are connected to the output terminals OUT1 and OUT2, respectively.
FIG. 8 shows an operation waveform of the pulse generating circuit 31. The first pulse in synchronization with the rising of the control input signal which is input to the input terminal IN and the second pulse in synchronization with falling thereof are output from the first output terminal OUT1 and the second output terminal OUT2, respectively.
The first pulse is input to a gate of an n-type high voltage MOSFET 32a, converted into a signal which is level-shifted by a resistance 33a, and input to a reset input R of an RS flip-flop 34. The second pulse is input to a gate of an n-type high voltage MOSFET 32b, converted into a signal which is level-shifted by a resistance 33b, and input to a set input S of the RS flip-flop 34. An output Q of the RS flip-flop 34 is connected to an input of an inverter 35, and an output of the inverter 35 is connected to a gate of the MOSFET 7a through the output terminal Vh.
As a result thereof, the control input signal which is input to the control input terminal Inh is level-shifted and transmitted to the high-side circuit 36 which is floating, and output to the gate of the MOSFET 7a as a high-side output signal. On the other hand, the control input signal on the low side, which is input to the control input terminal Inl on the low side, is output to a gate terminal of the MOSFET 7b through the output terminal V1 on the low side.
To a drain of the MOSFET 7a, a high-voltage power source of, for example, around 600 V is connected through a high-voltage power source terminal HV of the inverter circuit INV. A source of the MOSFET 7a and a drain of the MOSFET 7b are connected to the reference power source terminal Vs of the driver circuit 30 and an output terminal OUT of the inverter circuit INV, respectively. A source of the MOSFET 7b is connected to a ground terminal for output GND of the inverter circuit INV to be grounded.
One end of the condenser 9 is connected to a cathode terminal of the diode 8 and the positive voltage power source terminal Vb, the other end thereof is connected to the reference power source terminal Vs, and an anode terminal of the diode 8 is connected to the power source terminal VCC. A bootstrap circuit is configured by the diode 8 and the condenser 9. When the floating condenser 9 is charged with a power source voltage supplied through the power source terminal VCC of the inverter circuit INV which is connected to the power source terminal VCC and a potential of the reference power source terminal Vs rises through the MOSFET 7a, a high voltage is generated at the positive voltage power source terminal Vb due to electrostatic bonding through the condenser 9, so that floating power source supply is realized in the high-side circuit 36.
When two positive and reverse control input signals whose phases are inversed are input to the two control input terminals Inh and Inl, an output signal with a high voltage applied between the power source terminal HV and the ground terminal GND of the inverter circuit INV as an amplitude is generated on the output terminal OUT of the inverter circuit INV which is connected to the reference power source terminal Vs.
A reason why the pulse generating circuit 31 and the RS flip-flop 34 are used in the conventional circuit configuration shown in FIG. 6 is that power supplied by the bootstrap circuit to the condenser 9 is limited so that power consumption at the high-side circuit 36 is suppressed as much as possible to keep output capability of the inverter 35.
However, there is a problem that input of the RS flip-flop 34 is likely to be subjected to faulty operation with respect to noise, and countermeasure for noise is needed under a condition with much noise like the high-side circuit 36. Against such a problem, in PTL 1 described below, proposed is a circuit configuration in which a filter by a logic circuit is arranged before an RS flip-flop to prevent faulty operation due to noise.
Moreover, in PTL 2 described below, in order to provide a level shift circuit capable of suppressing faulty operation of an upper arm power switching element and an inverter device provided with the same, proposed is a method that in a series circuit of a resistance for generating an input signal of a power switching element driving circuit and an n-type MOSFET, each of the resistance and the n-type MOSFET is surrounded by double isolation oxide films and a potential of a Si active layer held between these double isolation oxide films is separately supplied. Specifically, with this method, when a time differentiation (dv/dt) of a low-level power source potential of the power switching element driving circuit which is connected to a source of the upper arm power switching element is generated, a voltage drop of this resistance is lowered to suppress faulty operation of the level shift circuit.